Consistency between circuit diagram, RTL code and waveform
What you’ll be taught
Widespread used Verilog syntaxes for design and verification
Descript mixture logic (fundamental logic gates, MUX, decoder, one-hot decoder)
Descript sequential logic (DFF with sync/async reset, ounter, edge detect, shift registers, sequence test, sync_fifo)
Design finite state machine (FSM)
Write testbench
Widespread errors for synthesis (incomplete delicate checklist, latch, multi-driven, mixture logic loop)
Observe time: z-scan, complicated sequence test (FSM)
Why take this course?
Fast grasp via examples and coding workout routines, in movies lower than 10 hours. After examine, you’ll be able to have the flexibility of consistency between circuit schematic, Verilog code and waveform. That’s given anybody of them, you’ll be able to work out the opposite two. On this chapter (can be divided to a number of free sections), I’ll clarify:
1: Digital IP/IC design circulate;
2: Fast evaluation of digital elementary
3: Set up Verilator and GTKwave
4: Widespread used Verilog syntax for design and verification
5: Design mixture logic(fundamental gates, MUX, decoder, one-hot decoder)
6: Design sequential logic(sync-DFF, async-DFF)
7: Design small however helpful block(counter, edge detect, shift registers, sequence test, sync_fifo)
8: Design FSM(finite state machine)
9: Design fundamental testbench
10: Widespread errors for synthesis(incomplete delicate checklist, latch, multi-driven, mixture logic loop)
11: Observe time: design and confirm z-scan and sophisticated sequence test(FSM)
That is chapter 2, part 4 of entire Digital IC and FPGA design course.
In the entire course, I’ll introduce fundamentals of digital IC and FPGA design, with 12+ coding workout routines and three course tasks.
Principle half: MOS transistor -> logic cells -> arithmetic knowledge path -> Verilog language -> widespread used HW operate blocks and structure -> STA -> on-chip-bus(APB/AHB-Lite/AXI4) -> low energy design -> DFT -> SOC(MCU stage).
Perform blocks and structure: FSM, pipeline, arbiter, CDC, sync_fifo, async_fifo, ping-pong, pipeline with management, slide window, pipeline hazard and ahead path, systolic.
Venture: SHA-256 algorithm with easy interface, SHA-256 with APB/AXI interface, 2D DMA controller with APB/AXI interface.
After explaining of every HW structure, I provides you with a coding train, with reference code. Coding issue will start from a number of strains to fifty strains, greater than 100 strains, then round 200 strains. Whereas the ultimate massive challenge can be 1000+ strains.
I suppose these ought to be important data and expertise you want grasp to enter this space.
I’ll attempt my finest to clarify what-> how-> why and encourage you to do it higher on this course.
Please browse to my homepage on Udemy to acquire details about every chapter of this course.
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