IC/FPGA Design P2-S3: Verilog for Design and Verification

Destiny For Everything


Consistency between circuit diagram, RTL code and waveform

What you’ll study

Widespread used Verilog syntaxes for design and verification

Descript mixture logic (primary logic gates, MUX, decoder, one-hot decoder)

Descript sequential logic (DFF with sync/async reset, ounter, edge detect, shift registers, sequence examine, sync_fifo)

Design finite state machine (FSM)

Write testbench

Utilizing Verilator and GTKwave to debug a design

Widespread errors for synthesis (incomplete delicate record, latch, multi-driven, mixture logic loop)

Apply time: z-scan, advanced sequence examine (FSM)

Why take this course?

Fast grasp by examples and coding workout routines, in movies lower than 10 hours. After research, you may have the flexibility of consistency between circuit schematic, Verilog code and waveform. That’s given anybody of them, you may work out the opposite two. On this chapter (shall be divided to a number of free sections), I’ll clarify:

1: Digital IP/IC design move;

2: Fast evaluate of digital elementary

3: Set up Verilator and GTKwave

4: Widespread used Verilog syntax for design and verification

5: Design mixture logic(primary gates, MUX, decoder, one-hot decoder)

6: Design sequential logic(sync-DFF, async-DFF)

7: Design small however helpful block(counter, edge detect, shift registers, sequence examine, sync_fifo)

8: Design FSM(finite state machine)

9: Design primary testbench

10: Widespread errors for synthesis(incomplete delicate record, latch, multi-driven, mixture logic loop)

11: Apply time: design and confirm z-scan and complicated sequence examine(FSM)

That is chapter 2, part 3 of complete Digital IC and FPGA design course.

In the entire course, I’ll introduce fundamentals of digital IC and FPGA design, with 12+ coding workout routines and three course initiatives.

Principle half: MOS transistor -> logic cells -> arithmetic information path -> Verilog language -> frequent used HW operate blocks and structure -> STA -> on-chip-bus(APB/AHB-Lite/AXI4) -> low energy design -> DFT -> SOC(MCU degree).

Operate blocks and structure: FSM, pipeline, arbiter, CDC, sync_fifo, async_fifo, ping-pong, pipeline with management, slide window, pipeline hazard and ahead path, systolic.

Challenge: SHA-256 algorithm with easy interface, SHA-256 with APB/AXI interface, 2D DMA controller with APB/AXI interface.

After explaining of every HW structure, I gives you a coding train, with reference code. Coding problem will start from a number of traces to fifty traces, greater than 100 traces, then round 200 traces. Whereas the ultimate huge venture shall be 1000+ traces.

I suppose these must be important data and expertise you want grasp to enter this space.

I’ll strive my finest to elucidate what-> how-> why and encourage you to do it higher on this course.

Please browse to my homepage on Udemy to acquire details about every chapter of this course.

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