Consistency between circuit diagram, RTL code and waveform
What you’ll study
Frequent used Verilog syntaxes for design and verification
Descript mixture logic (primary logic gates, MUX, decoder, one-hot decoder)
Descript sequential logic (DFF with sync/async reset, ounter, edge detect, shift registers, sequence verify, sync_fifo)
Design finite state machine (FSM)
Write testbench
Utilizing Verilator and GTKwave to debug a design
Frequent errors for synthesis (incomplete delicate checklist, latch, multi-driven, mixture logic loop)
Apply time: z-scan, complicated sequence verify (FSM)
Why take this course?
Fast grasp by means of examples and coding workout routines, in movies lower than 10 hours. After examine, you’ll be able to have the power of consistency between circuit schematic, Verilog code and waveform. That’s given anybody of them, you’ll be able to work out the opposite two. On this chapter (might be divided to a number of free sections), I’ll clarify:
1: Digital IP/IC design stream;
2: Fast evaluation of digital elementary
3: Set up Verilator and GTKwave
4: Frequent used Verilog syntax for design and verification
5: Design mixture logic(primary gates, MUX, decoder, one-hot decoder)
6: Design sequential logic(sync-DFF, async-DFF)
7: Design small however helpful block(counter, edge detect, shift registers, sequence verify, sync_fifo)
8: Design FSM(finite state machine)
9: Design primary testbench
10: Frequent errors for synthesis(incomplete delicate checklist, latch, multi-driven, mixture logic loop)
11: Apply time: design and confirm z-scan and complicated sequence verify(FSM)
That is chapter 2, part 2 of entire Digital IC and FPGA design course.
In the entire course, I’ll introduce fundamentals of digital IC and FPGA design, with 12+ coding workout routines and three course tasks.
Idea half: MOS transistor -> logic cells -> arithmetic knowledge path -> Verilog language -> widespread used HW operate blocks and structure -> STA -> on-chip-bus(APB/AHB-Lite/AXI4) -> low energy design -> DFT -> SOC(MCU degree).
Perform blocks and structure: FSM, pipeline, arbiter, CDC, sync_fifo, async_fifo, ping-pong, pipeline with management, slide window, pipeline hazard and ahead path, systolic.
Mission: SHA-256 algorithm with easy interface, SHA-256 with APB/AXI interface, 2D DMA controller with APB/AXI interface.
After explaining of every HW structure, I will provide you with a coding train, with reference code. Coding issue will start from a number of traces to fifty traces, greater than 100 traces, then round 200 traces. Whereas the ultimate massive mission might be 1000+ traces.
I suppose these must be important information and expertise you want grasp to enter this space.
I’ll strive my greatest to clarify what-> how-> why and encourage you to do it higher on this course.
Please browse to my homepage on Udemy to acquire details about every chapter of this course.
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